`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: DreamerT
// 
// Create Date: 2022/06/20 19:24:26
// Design Name: FPGA-Timer
// 
//////////////////////////////////////////////////////////////////////////////////


module Timer_top(
    input clk, //100Mhz
    input set, //button
    output [23:0] bit_out
    );
    wire msc; //T=10ms clock

    //o0:00:00 ~ 99:59:59
    wire [6:0]ms; //00~99
    wire [5:0]s;  //00~59
    wire [6:0]m;  //00~99
    
    //get T=10ms clock
    tick u0(.clk(clk),.msc(msc));
    //control & timing
    timer u1(.msc(msc),.set(set),.ms(ms),.s(s),.m(m));

    wire [3:0]ms1;
    wire [3:0]ms2;
    wire [3:0]s1;
    wire [3:0]s2;
    wire [3:0]m1;
    wire [3:0]m2;

    //separate tens and ones
    changer u4(.src(ms),.ten(ms1),.one(ms2));
    changer u5(.src(s),.ten(s1),.one(s2));
    changer u6(.src(m),.ten(m1),.one(m2));
    
    //scan to display
    flash_rate u3(
        .clk(clk),.ms1(ms1),.ms2(ms2),
        .s1(s1),.s2(s2),
        .m1(m1),.m2(m2),
        .bit_out(bit_out));
    
endmodule
